The present invention relates to an etching method for forming holes having a high aspect ratio in a silicon oxide film formed on a substrate via a silicon nitride film.
With increasing reduction in the size of semiconductor devices, the amount of displacement in alignment of masks placed one upon the other has become too critical to be negligible. For example, if the amount of displacement in alignment of masks for gate interconnections and contact holes is great, a gate interconnection and a conductive film with which a contact hole is filled may disadvantageously be short-circuited, causing a failure of operation of the device.
To overcome the above problem, an etching method called a self-aligning contact etching method has been proposed. This etching method will be described with reference to FIG. 9A.
Referring to FIG. 9A, gate interconnections (gate electrodes) 103 composed of a polysilicon film are formed on a silicon substrate 100 via a gate insulating film 102. The silicon substrate 100 includes a cobalt silicide layer 101 formed over a source/drain region. A silicon nitride film 104 having a thickness of 10 to 80 nm is deposited on the space between the gate interconnections 103 and the top and side faces of the gate interconnections 103. A silicon oxide film 105 is formed over the silicon nitride film 104.
The silicon oxide film 105 is subjected to plasma etching via a mask of a resist pattern 106 having hole formation openings, to form a contact hole 107 though the silicon oxide film 105 so that the contact hole 107 is positioned at the space between the gate interconnections 103.
In the above etching, the portion of the silicon oxide film 105 deposited in the space between the gate interconnections 103 must be etched away while the portions of the silicon nitride film 104 deposited on the side faces of the gate interconnections 103 are kept from etching. This disadvantageously reduces the margin of the etching time.
In addition, after the removal of the portion of the silicon oxide film 105 in the space between the gate interconnections 103 by etching, the portion of the silicon nitride film 104 exposed on the bottom of the contact hole 107 must be etched away to expose the cobalt silicide layer 101. During this etching, the portions of the silicon nitride film 104 on the side faces of the gate interconnections 103 may also be etched and this may possibly result in exposure of the gate interconnections 103 to the contact hole 107.
To prevent the above problem, proposed has been a method of etching the silicon oxide film 105 with an etching gas containing fluorocarbon gas, such as an etching gas composed of a mixture of Ar gas, O2 gas and C5F8 gas, for example.
By use of such an etching gas composed of a mixture of Ar gas, O2 gas and C5F8 gas for etching of the silicon oxide film 105, a deposition attaches to the wall of the contact hole 107 forming a deposition layer throughout the etching. This enables securing of a margin of the etching time and also eliminates the possibility of exposure of the gate interconnections 103 to the contact hole 107.
However, with increase of the aspect ratio of the contact hole 107, the growth of the deposition layer on the wall of the contact hole 107 may exceed the progress of the etching of the portion of the silicon oxide film 105 on the bottom of the contact hole 107. As a result, this may stop the etching of the portion of the silicon oxide film 105 on the bottom of the contact hole 107, as shown in FIG. 9B.